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19-3408; Rev 0; 8/04
MAX1213 Evaluation Kit
General Description
The MAX1213 evaluation kit (EV kit) is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX1213 analog-to-digital converter (ADC). The MAX1213 accepts differential analog inputs; however, the EV kit generates this signal from a user-provided single-ended signal source. The digital outputs produced by the ADC can be easily captured with a userprovided high-speed logic analyzer or data-acquisition system. The EV kit operates from 1.8V power supplies and includes circuitry that generates a clock signal from a user-provided AC signal. o Up to 170Msps Sampling Rate o Low-Voltage and Low-Power Operation o Fully Differential Signal Input Configuration o On-Board Differential Output Drivers o Fully Assembled and Tested
Features
Evaluates: MAX1213
Ordering Information
PART MAX1213EVKIT TEMP RANGE 0C to +70C IC PACKAGE 68 QFN-EP*
*EP = Exposed pad.
Component List
DESIGNATION C1-C11, C13, C15, C16, C18, C19, C20, C36-C39 C12, C14, C17 C21-C24 QTY 21 0 4 DESCRIPTION 0.1F 10%, 10V X5R ceramic capacitors (0402) TDK C1005X5R1A104K Not installed, capacitors (0402) 0.22F 10%, 6.3V X5R ceramic capacitors (0402) TDK C1005X5R0J224K Not installed, shorted by PC trace (0603) 47F 10%, 10V tantalum capacitors (C case) AVX TAJC476K010 10F 20%, 6.3V X5R ceramic capacitors (0805) TDK C2012X5R0J106M 22F 10%, 6.3V X5R ceramic capacitor (0805) TDK C2012X5R0J226K Not installed, capacitor (0805) 1.0F 10%, 10V X5R ceramic capacitors (0603) TDK C1608X5R1A105K 2.2F 10%, 6.3V X5R ceramic capacitor (0603) TDK C1608X5R0J225K Not installed, capacitor (0603) DESIGNATION C35 QTY 1 DESCRIPTION 0.01F 20%, 25V X7R ceramic capacitor (0402) TDK C1005X7R1E103M SMA PC board vertical-mount connectors Not installed, vertical SMA connector Dual-row 8-pin header Dual-row 40-pin headers 3-pin headers Not installed, resistors (0603) 49.9 1% resistor (0603) 150 5% resistors (0603) 24.9 0.1% resistors (0603) IRC PFC-W0603R-02-24R9-B 0 resistors (0603) 10 1% resistors (0603) 100 1% resistors (0603) 100 5% resistors (0603) 510 5% resistors (0603) 510 5% resistors (0402) 100k, 12-turn, 1/4in potentiometer 13k 1% resistor (0603)
J1, CLK J2 J3 J4-J7 JU1, JU2, JU3 R1, R3, R6, R7, R11, R13, R14, R15, R43 R2 R4, R5 R8, R9
2 0 1 4 3 0 1 2 2 2 2 14 4 2 28 1 1
C25, C26
0
C27, C28, C40
3
C29, C41
2
C30 C31 C32, C42
1 0 2
R10, R12 R16, R17 R18-R24, R28-R32, R34, R35 R25, R26, R27, R33 R36, R37 R38, R39, R41, R44-R68 R40 R42
C33 C34
1 0
________________________________________________________________ Maxim Integrated Products
1
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MAX1213 Evaluation Kit Evaluates: MAX1213
Component List (continued)
DESIGNATION T1, T2 TP1, TP2 U1 QTY 2 2 1 DESCRIPTION 1:1 800MHz RF transformers Mini-Circuits ADT1-1WT Test points (black) MAX1213EGK (68-pin QFN, 10mm x 10mm) 3.3V ECL differential receiver (8-pin SO) ON Semiconductor MC100LVEL16D Y1 None 0 1 DESIGNATION QTY DESCRIPTION 3.3V ECL quad differential receivers (20-pin SO) ON Semiconductor MC100LVEL17DW Not installed, clock oscillator MAX1213 PC board
U3-U6
4
U2
1
Component Suppliers
SUPPLIER AVX IRC TDK PHONE 843-946-0238 361-992-7900 847-803-6100 FAX 843-626-3123 361-992-3377 847-390-4405 WEBSITE www.avxcorp.com www.irctt.com www.component.tdk.com
Note: Indicate that you are using the MAX1213 when contacting these component suppliers.
Quick Start
Recommended Equipment
* DC power supplies: Analog (VCC) 1.8V, 1A 2) 3) 4)
Clock (VCLK) 3.3V, 200mA Buffers (VLPEL) 3.3V, 400mA * Signal generator with low-phase noise and low jitter for clock input (e.g., HP 8662A, HP 8644B) * Signal generator for analog signal input (e.g., HP 8662A, HP 8644B) * Logic analyzer or data-acquisition system (e.g., HP 16500C with high-speed state card HP 16517A) * Digital voltmeter
5)
Procedure
The MAX1213 EV kit is a fully assembled and tested surface-mount board. Follow the steps below for board operation. Do not turn on power supplies or enable signal generators until all connections are completed: 1) Verify that shunts are installed in the following locations:
6)
7)
8)
JU2 (1-2) divide-by-two disabled JU3 (2-3) two's-complement output selected J3 (3-4) internal reference enabled Connect the clock signal generator to the SMA connector labeled CLK. Connect the analog input signal generator to the SMA connector labeled J1. Connect the logic analyzer with high-speed card probe to either headers J4/J5 (LVDS-compatible signals) or J6/J7 (LVPECL-compatible signals). See Table 4 for header connections. Connect a 1.8V, 1A power supply to VCC. Connect the ground terminal of this supply to GND closest to the VCC pad. Connect a 3.3V, 200mA power supply to VCLK. Connect the ground terminal of this supply to GND closest to the VCLK pad. Connect a 3.3V, 400mA power supply to VLPEL. Connect the ground terminal of this supply to GND closest to the VLPEL pad. Turn on all power supplies.
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MAX1213 Evaluation Kit
9) Enable the signal generators. Set the clock signal generator to output a 170MHz signal, with an amplitude of 2.4VP-P. Set the analog input signal generator to output the desired frequency with an amplitude 2VP-P. The signal generators should be synchronized. available, the EV kit's on-board level translator helps to convert a singled-ended clock signal to the required differential signal. An on-board clock-shaping circuit generates a differential clock signal from an AC sinewave signal applied to the clock input SMA connector (CLK). The input signal should not exceed an amplitude of 2.6VP-P. The frequency of the sinusoidal input clock signal determines the sampling frequency (fCLK) of the ADC. A differential line receiver (U2) processes the input signal to generate the required clock signal. The frequency of the clock signal should not exceed 170MHz. Clock Divider The MAX1213 features an internal divide-by-two clock divider. Use jumper JU2 to enable/disable this feature. See Table 1 for shunt positions.
Evaluates: MAX1213
10) Enable the logic analyzer. 11) Collect data using the logic analyzer.
Detailed Description
The MAX1213 EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX1213, 12-bit LVDS output ADC. The MAX1213 can be evaluated with a maximum clock frequency (fCLK) of 170MHz. The MAX1213 accepts differential inputs. Applications that only have a single-ended signal source available can use the on-board transformer (T2) to convert the singled-ended signal to a differential signal. Output level translators (U3-U6) buffer and convert the LVDS output signals of the MAX1213 to higher voltage LVPECL signals that can be captured by a wide variety of logic analyzers. The LVDS outputs are accessed at headers J4 and J5. The LVPECL outputs are accessed at headers J6 and J7. The EV kit is designed as a four-layer PC board to optimize the performance of the MAX1213. Separate analog, clock, and buffer power planes minimize noise coupling between analog and digital signals; 50 coplanar transmission lines are used for analog and clock inputs and 100 differential coplanar transmission lines are used for all digital LVDS outputs. All LVDS differential outputs are properly terminated with 100 termination resistors between true and complementary digital outputs. The trace lengths of the 100 differential LVDS lines are matched to within a few thousandths of an inch to minimize layout-dependent delays.
Table 1. Clock-Divider Shunt Settings (JU2)
SHUNT POSITION 1-2 (default) 2-3 MAX1213 CLKDIV PIN Connected to VCC Connected to GND DESCRIPTION Clock signal divided by 1 Clock signal divided by 2
Input Signal
The MAX1213 accepts differential analog input signals. However, the EV kit only requires a single-ended analog input signal with an amplitude of less than 2VP-P provided by the user. An on-board transformer then takes the single-ended analog input and generates a differential analog signal, which is applied to the ADC's differential input pins. Optional Input Transformer The MAX1213 EV kit uses a second transformer to enhance THD and SFDR performance at high input frequencies (>100MHz). This transformer helps to reduce the increase of even-order harmonics at high frequencies. To use only the primary transformer, follow the directions below: 1) Remove R10 and R12. 2) Install a 0.1F capacitor on C14. 3) Connect the analog signal source to J2 instead of J1.
Power Supplies
The MAX1213 EV kit requires separate analog, clock, and buffer power supplies for best performance. A 1.8V power supply is used to power the analog and digital portion of the MAX1213. The on-board clock circuitry is powered by a 3.3V power supply. A separate 3.3V power supply is used to power the output buffers (U3-U6) on the EV kit.
Clock
The MAX1213 requires a differential clock signal. However, if only a single-ended clock signal source is
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MAX1213 Evaluation Kit Evaluates: MAX1213
Reference Voltage
There are two methods to set the full-scale range of the MAX1213. The MAX1213 EV kit can be configured to use the ADC's internal reference, or a stable, low-noise, external reference can be applied to the REFIO pad. Jumper J3 controls which reference source is used. See Table 2 for shunt settings. Output Format The digital output coding can be chosen to be either in two's complement or straight offset binary format by configuring jumper JU3. See Table 3 for shunt settings.
Table 3. Output-Format Shunt Settings (JU3)
SHUNT POSITION 1-2 2-3 (default) MAX1213 T/B Pin Connected to VCC Connected to GND DESCRIPTION Digital output in straight offset binary Digital output in two's complement
Table 2. Reference Shunt Settings (J3)
SHUNT POSITION 1-2 3-4 (default) 5-6 7-8 DESCRIPTION Internal reference disabled. Apply an external reference voltage to the REFIO pad. Internal reference enabled. Increases FSR through the trim potentiometer R40. Decreases FSR through the trim potentiometer R40.
Output Signal
The MAX1213 features a single 12-bit, parallel, LVDScompatible, digital output bus. The digital outputs also feature a clock bit (DCOP/N) for data synchronization, and a data overrange bit (ORP/N). See Table 4 for header connections.
Output Bit Locations The digital outputs of the ADC are connected to two 40pin headers (J4 and J5). PC board trace lengths are matched to minimize output skew and improve performance of the device. In addition, four drivers (U3-U6) buffer and level translate the ADC's digital outputs to LVPECL-compatible signals. The drivers increase the differential voltage swing and are able to drive large capacitive loads, which may be present at the logic analyzer connection. The outputs of the buffers are connected to two 40-pin headers (J6 and J7). See Table 4 for headers J4-J7 bit locations.
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MAX1213 Evaluation Kit Evaluates: MAX1213
Table 4. Output Bit Locations
BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OR DCO P N P N P N P N P N P N P N P N P N P N P N P N P N P N UNBUFFERED (LVDS) J6-10 J6-9 J6-16 J6-15 J6-22 J6-21 J6-28 J6-27 J6-34 J6-33 J6-40 J6-39 J7-8 J7-7 J7-14 J7-13 J7-20 J7-19 J7-26 J7-25 J7-32 J7-31 J7-38 J7-37 J6-4 J6-3 J7-2 J7-1 BUFFERED (LVPECL) J4-10 J4-9 J4-16 J4-15 J4-22 J4-21 J4-28 J4-27 J4-34 J4-33 J4-40 J4-39 J5-8 J5-7 J5-14 J5-13 J5-20 J5-19 J5-26 J5-25 J5-32 J5-31 J5-38 J5-37 J4-4 J4-3 J5-2 J5-1 P N P N P N P N P N P N P N P N P N P N P N P N P N P N BIT LD11 LD10 LD9 LD8 LD7 LD6 Data bits LD5 LD4 LD3 LD2 LD1 LD0 LOR LDC0 LSB Overrange bit Clock output signal DESCRIPTION MSB
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5
MAX1213 Evaluation Kit Evaluates: MAX1213
VCC
VCC
C1 0.1F
C2 0.1F
C22 0.22F
C23 0.22F
C6 0.1F
C7 0.1F
C24 0.22F
C8 0.1F
1 6 11 12 13 14 20 25 62 63 65 AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC
27 28 41 44 60 OVCC OVCC OVCC OVCC OVCC
ORP ORN 59 R18 100 1% ORN D11P R19 100 1% D11N D10P R20 100 1% D10N D9P R21 100 1% D9N D8P R22 100 1% D8N D7P R23 100 1% D7N D6P R24 100 1% D6N DCOP R28 100 1% DCON D5P R29 100 1% D5N D4P R30 100 1% D4N D3P R31 100 1% D3N D2P R32 100 1% D2N D1P R34 100 1% D1N D0P R35 100 1% D0N VCC GND D2P D2N D3P D3N D4P D4N D5P D5N DCOP DCON D6P D6N D7P D7N D8P D8N D9P D9N D10P D10N ORP D11P D11N
J4-4 J4-3 J4-1 J4-10 J4-9 J4-11 J4-16 J4-15 J4-17 J4-22 J4-21 J4-23 J4-28 J4-27 J4-29 J4-34 J4-33 J4-35 J4-40 J4-39
J4-2 J4-5 J4-6 J4-8 J4-7 J4-12 J4-14 J4-13 J4-18 J4-20 J4-19 J4-24 J4-26 J4-25 J4-30 J4-32 J4-31 J4-36 J4-38 J4-37
J4
PLACE CAPACITORS NEXT TO PINS 1, 6, 11/12, 13/14, 20, 25, 62/63, 65 OF U1. C9 0.1F 1 5 3 R16 C25 10 SHORT 1% 6 2 4 R8 24.9 TP1 0.1% R9 24.9 0.1% C26 SHORT R17 10 1% C11 0.1F 9 C17 OPEN
ORP
J1
R10 0 T1 4 2 6 R7 OPEN C10 0.1F R6 OPEN R43 OPEN 3 5 1
R11 OPEN T2
8 C12 OPEN
INP
ORN D11P
58 57
R1 OPEN
D11N D10P INN D10N D9P 22 CLKP D9N D8P
56 55
J2
C14 OPEN
R12 0
R13 OPEN
54 53
R3 OPEN
VCLK C15 0.1F C13 0.1F 2 R2 49.9 1% R37 510 D U2 MC100LVEL16 3 R36 510 D Q VBB 4 C35 0.01F VEE 5 6 R5 150 1 N.C. 8 VCC Q
CLKP
C16 0.1F
52 51
CLK
7 R4 150 CLKN D8N 23 C19 0.1F CLKN D7P 50 49
U1
D7N 48 47
MAX1213
D6P
J5-2 J5-1 J5-5 J5-8 J5-7 J5-11 J5-14 J5-13 J5-17 J5-20 J5-19 J5-23 J5-26 J5-25 J5-29
J5-3 J5-4 J5-6 J5-9 J5-10 J5-12 J5-15 J5-16 J5-18 J5-21 J5-22 J5-24 J5-27 J5-28 J5-30 J5-33 J5-34 J5-36 J5-39 J5-40 VCLK
J5
D6N DCLKP
46 43
VCLK C18 0.1F 6 VCC N.C. Y1 VF561E OPEN 2 5 OUT
VCLK
R25 100 4 VCLK R26 100
1
R14 OPEN CLKP
DCLKN D5P
42 40
VCLK 1 2 3
D5N R27 100 R15 OPEN CLKN R33 100 VCC 1 2 3 VCC 1 2 68 3 D3N 17 CLKDIV D2P D4N T/B D3P D4P
39 38
JU1
OE GND 3
OUT
37 36
JU3
35 34
JU2
D1P D1N
J5-32 J5-31 J5-35
J3 REFADJ J3-1 J3-3 RJ J3-5 J3-7 VCC J3-2 J3-4 J3-6 J3-8
VCC D2N REFADJ REFI0 3 C20 0.1F 4 REFADJ REFI0 D1N D0P 31 30 D1P 33 32
D0P D0N
J5-38 J5-37
3
R40 100k 2
R42 13k 1%
VCLK GND C27 47F 10V C29 10F C32 1.0F
RJ C21 0.22F C3 0.1F C4 0.1F C5 0.1F
1
D0N REF ADJ TP2 OGND OGND OGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND
29
VCC
PLACE CAPACITORS NEXT TO PINS 27/28, 41, 44, 60, OF U1.
16 2
5
7 10 15 18 19 21 24 64 66 67
26 45 61
C28 47F 10V
C30 22F
C33 2.2F
C31 OPEN
C34 OPEN
Figure 1. MAX1213 EV Kit Schematic (Sheet 1 of 2)
6
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MAX1213 Evaluation Kit Evaluates: MAX1213
VLPEL C36 0.1F 1 VCC D0 20 VCC 19 Q0 R41 510 D0 R44 510 D1 Q0 Q1 D11N 5 D1 U3 MC100LVEL17 18 17 R45 510 R46 510 Q1 D2 Q2 16 15 R47 510 R48 510 Q2 Q3 14 13 R49 510 R50 510 Q3 VEE 11 12 BD9N VBB 10 BD10N BD9P BD11N BD10P D6N BORN BD11P D7N 5 D1 D7P D8N 1 VCC D0
VLPEL C38 0.1F 20 VCC 19 Q0 R38 510 D0 R39 510 D1 Q0 Q1 U4 MC100LVEL17 18 17 R51 510 R52 510 Q1 D2 Q2 16 15 R53 510 R54 510 Q2 Q3 14 13 BD6N BD7N BD6P D4N BD8N BD7P D5N 5 D1 D5P DCON 1 VCC D0
VLPEL C37 0.1F 20 VCC 19 Q0 R57 510 D0 R58 510 D1 Q0 Q1 U5 MC100LVEL17 18 17 R59 510 R60 510 Q1 D2 Q2 16 15 R61 510 R62 510 Q2 Q3 14 13 R63 510 R64 510 BD4N BD3P BD5N BD4P D0N BDCON BD5P D1N 5 D1 D1P D2N 1 VCC D0
VLPEL C39 0.1F 20 VCC 19 Q0 R55 510 D0 R56 510 D1 Q0 Q1 U6 MC100LVEL17 18 17 R65 510 R66 510 Q1 D2 Q2 16 15 R67 510 R68 510 Q2 Q3 14 13 BD0N BD1N BD0P BD2N BD1P
ORP
2
BORP
D8P
2
BD8P
DCOP
2
BDCOP
D2P
2
BD2P
ORN
3
3
3
3
D11P
4
4
4
4
D10P
6
D2
D6P
6
D2
D4P
6
D2
D0P
6
D2
D10N
7
7
7
7
D9P
8
D3
8
D3
D3P
8
D3
8
D3
D9N
9
D3
9
D3
D3N
9
D3
9
D3
Q3 VEE 11
12 VBB 10
VBB 10
Q3 VEE 11
12
BD3N VBB 10 11
Q3 VEE
12
VLPEL BORP BORN J6-4 J6-3 J6-1 BD11P BD11N J6-10 J6-9 J6-11 BD10P BD10N J6-16 J6-15 J6-17 BD9P BD9N J6-22 J6-21 J6-23 BD8P BD8N J6-28 J6-27 J6-29 BD7P BD7N J6-34 J6-33 J6-35 BD6P BD6N J6-40 J6-39 J6-2 J6-5 J6-6 J6-8 J6-7 J6-12 J6-14 J6-13 J6-18 J6-20 J6-19 J6-24 J6-26 J6-25 J6-30 J6-32 J6-31 J6-36 J6-38 J6-37 BD0P BD0N BD1P BD1N BD2P BD2N BD3P BD3N BD4P BD4N BD5P BD5N J6 BDC0P BDC0N J7-2 J7-1 J7-5 J7-8 J7-7 J7-11 J7-14 J7-13 J7-17 J7-20 J7-19 J7-23 J7-26 J7-25 J7-29 J7-32 J7-31 J7-35 J7-38 J7-37 J7-3 J7-4 J7-6 J7-9 J7-10 J7-12 J7-15 J7-16 J7-18 J7-21 J7-22 J7-24 J7-27 J7-28 J7-30 J7-33 J7-34 J7-36 J7-39 J7-40 GND J7 VLPEL C40 47F 10V C41 10F C42 1.0F
Figure 1. MAX1213 EV Kit Schematic (Sheet 2 of 2) _______________________________________________________________________________________ 7
MAX1213 Evaluation Kit Evaluates: MAX1213
Figure 2. MAX1213 EV Kit Component Placement Guide--Component Side 8 _______________________________________________________________________________________
MAX1213 Evaluation Kit Evaluates: MAX1213
Figure 3. MAX1213 EV Kit PC Board Layout--Component Side
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MAX1213 Evaluation Kit Evaluates: MAX1213
Figure 4. MAX1213 EV Kit PC Board Layout--Ground Plane 10 ______________________________________________________________________________________
MAX1213 Evaluation Kit Evaluates: MAX1213
Figure 5. MAX1213 EV Kit PC Board Layout--Power Planes
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11
MAX1213 Evaluation Kit Evaluates: MAX1213
Figure 6. MAX1213 EV Kit PC Board Layout--Solder Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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